Ajit K Mylavarapu

8392651, Mar 5, 2013

Aug 20, 2008

12/194936

Ajit Karthik Mylavarapu - Mountain View CA, US

MIPS Technologies, Inc. - Sunnyvale CA

G06F 12/00
G06F 13/00
G06F 13/28

711108, 711128, 711E12018, 711E12069, 711E12083

A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N−1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.

20100049953, Feb 25, 2010

Aug 20, 2008

12/195053

Ajit Karthik Mylavarapu - Mountain View CA, US
Sanjai Balakrishnan Athi - Santa Clara CA, US

MIPS Technologies, Inc. - Mountain View CA

G06F 9/312

712225, 712E09033

A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index line in which the requested data is stored. The logic block further provides a disabling signal to the N-way cache for at least one clock cycle if the first and second instructions are detected as pointing to the same cache way.