Benjamin P Colombeau

8101487, Jan 24, 2012

May 15, 2009

12/466391

Dexter Xueming Tan - Singapore, SG
Benjamin Colombeau - Salem MA, US
Clark Kuang Kian Ong - Singapore, SG
Sai Hooi Yeong - Singapore, SG
Chee Mang Ng - Singapore, SG
Kin Leong Pey - Singapore, SG

Nanyang Technological University - Singapore
National University of Singapore - Singapore
GLOBALFOUNDRIES Singapore Pte. Ltd. - Singapore

H01L 21/336
H01L 21/3205
H01L 21/4763

438301, 438305, 438308, 438591

A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

8101528, Jan 24, 2012

Aug 4, 2010

12/850317

Christopher R. Hatem - Salisbury MA, US
Benjamin Colombeau - Salem MA, US

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

H01L 21/31

438766, 438302, 438369, 438480, 438505

A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.

8293544, Oct 23, 2012

Jul 28, 2008

12/220792

Debora Chyiu Hyia Poon - Singapore, SG
Alex Kh See - Singapore, SG
Francis Benistant - Singapore, SG
Benjamin Colombeau - Salem MA, US
Yun Ling Tan - Singapore, SG
Mei Sheng Zhou - Singapore, SG
Liang Choo Hsia - Singapore, SG

GlobalFoundries Singapore Pte. Ltd. - Singapore

H01L 21/00

438 5, 257E2153

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e. g. , a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

20110033998, Feb 10, 2011

Aug 5, 2010

12/851141

Christopher R. Hatem - Salisbury MA, US
Benjamin Colombeau - Salem MA, US
Thirumal Thanigaivelan - North Andover MA, US
Dennis Rodier - Francestown NH, US

VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. - Gloucester MA

H01L 21/22

438302, 257E21135

An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.

20110034014, Feb 10, 2011

Aug 4, 2010

12/850271

Christopher R. Hatem - Salisbury MA, US
Benjamin Colombeau - Salem MA, US
Thirumal Thanigaivelan - North Andover MA, US
Jay T. Scheuer - Rowley MA, US

VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. - Gloucester MA

H01L 21/265
H01L 21/425
H01L 21/38

438530, 438514, 438914, 257E21334

A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.

20130099321, Apr 25, 2013

Oct 10, 2012

13/648905

Globalfoundries Singapore Pte. Ltd. - Singapore, SG
Alex KH See - Singapore, SG
Francis Benistant - Singapore, SG
Benjamin Colombeau - Salem MA, US
Yun Ling Tan - Singapore, SG
Mei Sheng Zhou - Singapore, SG
Liang Choo Hsia - Singapore, SG

Globalfoundries Singapore Pte. Ltd. - Singapore

H01L 27/088

257368

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

20130252349, Sep 26, 2013

Mar 22, 2012

13/426785

Nilay Anil Pradhan - Waltham MA, US
Stanislav S. Todorov - Topsfield MA, US
Kurt Decker-Lucke - South Hamilton MA, US
Klaus Petry - Merrimac MA, US
Benjamin Colombeau - Salem MA, US
Baonian Guo - Andover MA, US

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

H01L 21/02

438 4, 257E21002

A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.

20130313971, Nov 28, 2013

May 22, 2012

13/477253

Costel Biloiu - Rockport MA, US
Craig R. Chaney - Lanesville MA, US
Neil J. Bassom - Hamilton MA, US
Benjamin Colombeau - Salem MA, US
Dennis P. Rodier - Francestown NH, US

VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. - Gloucester MA

H01J 27/20

31511121, 31323131

In one embodiment, a method for generating an ion beam having gallium ions includes providing at least a portion of a gallium compound target in a plasma chamber, the gallium compound target comprising gallium and at least one additional element. The method also includes initiating a plasma in the plasma chamber using at least one gaseous species and providing a source of gaseous etchant species to react with the gallium compound target to form a volatile gallium species.