Pranay Koka

7895400, Feb 22, 2011

Sep 28, 2007

11/864507

Brian W. O'Krafka - Austin TX, US
Pranay Koka - Austin TX, US
Robert J. Kroeger - Waterloo, CA

Oracle America, Inc. - Redwood City CA

G06F 12/08

711141, 711143, 711E12039

Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.

7929526, Apr 19, 2011

Sep 28, 2007

11/864414

Robert J. Kroeger - Waterloo, CA
Brian W. O'Krafka - Austin TX, US
Pranay Koka - Austin TX, US

Oracle America, Inc. - Redwood City CA

H04L 12/28
H04L 12/56
G06F 15/16
G06F 9/26

370389, 370412, 709245, 711200

A system and method for sending a cache line of data in a single message is described. An instruction issued by a processor in a multiprocessor system includes an address of a message payload and an address of a destination. Each address is translated to a physical address and sent to a scalability interface associated with the processor and in communication with a system interconnect. Upon translation the payload of the instruction is written to the scalability interface and thereafter communicated to the destination. According to one embodiment, the translation of the payload address is accomplished by the processor while in another embodiment the translation occurs at the scalability interface.

8103165, Jan 24, 2012

Jul 18, 2008

12/176293

Brian W. O'Krafka - Austin TX, US
Pranay Koka - Austin TX, US
John E. Cunningham - San Diego CA, US
Ashok Krishnamoorthy - San Diego CA, US
Xuezhe Zheng - San Diego CA, US

Oracle America, Inc. - Redwood City CA

H04B 10/08
H04B 17/00

398 36, 398 30

A method of detecting transmission collisions in an optical data interconnect system. The method includes initiating a data transmission of a data signal from a transmitting node over the optical data channel, transmitting a first collision detect signal from the transmitting node throughout a duration of the data transmission where the first collision detect signal is transmitted over an optical detection channel corresponding to the transmitting node, monitoring at the transmitting node of the optical data interconnect system for a predetermined period of time, where the optical data interconnect system further includes optical collision detection channels corresponding to each of a plurality of receiving nodes and one or more remaining nodes, and identifying a transmission collision when a second collision signal is received through one of the optical collision detection channels at the transmitting node during the predetermined period of time.

8108631, Jan 31, 2012

Jul 18, 2008

12/176298

Pranay Koka - Austin TX, US
Brian W. O'Krafka - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 13/00
G06F 13/28
G06F 9/26
G06F 9/34

711154, 711141, 711206, 711210, 711E12014, 711E12034

A method, including: initiating a memory operation at a first node including a first memory controller (MC) and a transaction table configured to store a list of nodes affected by the memory operation, transmitting a store request signal to a second node including a second MC and an access table (AT) where the store request signal includes data from the first MC, storing data to the AT in entries corresponding to memory address(es) (MAs) affected by the memory operation, identifying a memory conflict with one or more nodes in the list of nodes when the MAs affected by the memory operation are also affected by one or more conflicting transactions listed in the AT, transmitting an abort signal from the second node to each of the nodes corresponding to the memory conflict, and transmitting an intent to commit signal from the first node to the second node.

8176220, May 8, 2012

Oct 1, 2009

12/572189

Pranay Koka - Austin TX, US
Michael Oliver McCracken - Austin TX, US
Jan Lodewijk Bonebakker - Amersfoort, NL

Oracle America, Inc. - Redwood City CA

G06F 13/00

710 22, 711103, 711118, 711154, 711203, 709217

A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

8180968, May 15, 2012

Mar 28, 2007

11/729527

Brian W. O'Krafka - Austin TX, US
Roy S. Moore - Austin TX, US
Pranay Koka - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 12/00

711135, 711113, 711118, 711133, 711134, 711143, 711144, 711145, 711154, 711159

The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.

8280251, Oct 2, 2012

Apr 20, 2009

12/426844

Pranay Koka - Austin TX, US
Xuezhe Zheng - San Diego CA, US

Oracle America, Inc. - Redwood City CA

H04J 14/00

398 45, 398 51

A system for transmitting data, including: a transmitter node having a setup path packet and multiple data packets; a receiver node connected to the transmitter node by a first optical channel (OC); and a first intermediate node having a first forwarding module and connected to the transmitter node by a second OC and to the receiver node by a third OC, where the transmitter node transmits the setup path packet and a first subset of the multiple data packets to the first intermediate node using the second OC, where the first forwarding module relays, in response to receiving the setup packet, the first subset to the receiver node by switching the first subset from the second OC to the third OC, and where the receiver node receives a second subset of the multiple data packets from the transmitter node using the first OC.

8285140, Oct 9, 2012

Mar 12, 2010

12/723591

Michael Oliver McCracken - Austin TX, US
Pranay Koka - Austin TX, US
Xuezhe Zheng - San Diego CA, US
Ashok Krishnamoorthy - San Diego CA, US

Oracle International Corporation - Redwood City CA

H04J 14/00

398 45, 398 46, 398 50, 398 51

A system including first and second sending nodes, a horizontal optical data link (ODL) having optical signals propagating in opposite directions in first and second waveguide segments, a vertical ODL having optical signals propagating in the same direction throughout third and fourth waveguide segments, a first optical output switch operatively connecting the first sending node and the first waveguide segment and configured to switch first data item onto the first waveguide segment during a first timeslot, a second optical output switch operatively connecting the second sending node and the second waveguide segment and configured to switch second data item onto the second waveguide segment during a second timeslot, and an optical coupler pair operatively connecting the first and second waveguide segments to the third and fourth waveguide segments, respectively, and redirecting the first and the second data items from the horizontal to the vertical ODL.